In the manufacture of semiconductor devices, it is often required to measure the width of a formed line pattern, and determine whether it meets a technological requirement, to ensure device performance. For example, in the manufacture of the gate of a Metal-Oxide-Semiconductor (MOS) transistor, or the word line or bit line of a memory chip, after the corresponding pattern is formed, the width of it is measured. In the prior art, generally, a Scanning Electron Microscope (SEM) or a Transmission Electron Microscope (TEM) is used to measure the width of a line pattern. TEMs have high measurement accuracy, but require a complex and time-consuming procedure of sample preparation, which limits their usage.
FIG. 1 illustrates a conventional method for line width measurement with a cross section and corresponding topography. The method comprises: providing a substrate 10, with raised line patterns 11 and 12 formed on the surface of it; using a SEM to obtain an image containing information about the topography of the substrate 10, the line pattern 11 and the line pattern 12; then, determining the widths of the line pattern 11 and the line pattern 12 from the image. The SEM creates the image by scanning the sample's surface with a beam of electrons, and detecting and amplifying the produced signals; as a result, the sidewalls of a line pattern, e.g., the line pattern 11, appear distorted in the image, making it difficult to definitely identify the edges of the sidewalls of the line pattern 11. In the prior art, the edge is defined as a point in the image at which the magnitude is the mean of the peak and the valley. For example, the edges of the sidewalls of the line pattern 11 are defined as points L1 and L2, where the magnitude is the mean of the peak and the valley. Then, the width of the line pattern 11 is defined as the distance between the points L1 and L2. However, the points L1 and L2 are not exactly the true edges of the line pattern 11, which contributes to measurement uncertainty, and results in low precision.
When the Critical Dimension (CD) of the semiconductor device shrinks, the width of the line pattern 11 is reduced, leading to a greater measurement uncertainty and a lower precision.